Basics of termination, reflections, and parallel termination for hardware and PCB design. Including practical considerations, simulations, and demos. PCBs by PCBWay www.pcbway.com
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[TIMESTAMPS]
00:00 Intro
00:55 Altium Designer
01:35 PCBWay
02:12 Termination Basics
05:42 Reflections
09:17 Parallel Termination
10:43 Practical Considerations
15:14 Simulation Demo
19:12 DDR3 Example
21:51 Outro
Welcome back! Looking forward to this.
Thanks a lot!
@@PhilsLabyes! When is the series termination video coming out? Soon? 🤞 Great stuff! 💪
Great video, looking forward to the rest of this series!
Thank you, Rick!
@@PhilsLab Phil there is a mass confusion over the difference between bead, choke and inductor. They all have inductance but are not the same thing. I still do not understand the difference between these.
Something that could also be a very interesting Topic is high speed Signaling with connectors. Would be interesting to know how fast one can go with the typical 0.1 inch connectors
Great idea, thank you!
Thank you for this!!! Excellent as always!
Thanks a lot for watching!
Great Video Phil! I have your advanced hardware course where you also went over these topics and gave some more detail, but this video is also great.
Thanks for the great video❤
this one is the best and to the point with great practical example and solved my many queries. thanks alot.
Thank you very much!
Wow, this is great!
Thanks Phil for this amazing video. Your explanations are a masterpiece.
Thank you, Leonardo!
I've recently been working on LVCMOS18 termination for a friend's 50MHz Z80 backplane project where there can be up to 8 cards (with arbitrary order and 0-8 slots populated), with varying load capacitances, connector stubs, and a fairly long max distance (>200mm card to card in the worst case). Super tricky and had to spend a lot of time figuring out things like drive current and termination strategies by reading a ton of appnotes and the PCI spec, and doing days of LTRA simulations in LTspice, so I'm very glad to see you doing this series to help reduce the learning curve for anyone else who finds themselves trying to tackle a similar situation.
Thanks! Sounds like an interesting project - hope all goes well with that! Currently doing a DDR4 design and also keeping my fingers crossed :)
Very useful, thank you!
Glad to hear that, thanks!
Really, I like your videos and hope to continue.
Thank you!
Hi Phil hope you are well and great video as always. I have questions: First when looking at trace length I assume we would not take into account the extra length to the termination resistors if after the last pin as per your example. Then I don’t know this one but would a cap with a Z matching the line Z and rising edge freq also work? 🤔
Thanks for the great video! I did have two hopefully simple questions. One was, could you expand on what it means when you say 'the driver is not strong enough to drive 50 ohms'? Also, why does the PCB house determine the line impedance? Isn't that something you can control with trace width/pour?
Useful? It’s mind-blowing. I’ve been programming for over 40 years and had no idea, despite dabbling in electronics and having a Ham license. This gives me such an appreciation for the EE behind it all.
Actually I have q . I am a beginner for the high speed design can I get to know what does programming 🤔 mean for pcb design.?
Big fan of your content. If you're open to suggestions; it would be great to have a series about making a real product with an FPGA such as Ice40 using only open source tools, all the way from part selection to schematic, PCB layout, and then programming/bring-up. Similar-ish to the Zynq series, but more hobbiest-oriented. The Zync videos are great but due to cost and complexity of the FPGA used are somewhat out of reach to amateurs/hobbiests such as myself.
please can you make a video about the lumped element thing you talked about . fantastic video btw learned a lot from your channel .
I was just starting to do some research on bus termination. Perfect timing!. I want to get the most out of an ISA style bus in a retro PC design. Is there anything in particular that I should focus on for a 5V system bus?
Awesome, glad to hear that! I'd check what others have done an ISA bus (I assume it won't require much in the way of termination), e.g. retrocomputing.stackexchange.com/questions/19880/how-do-i-terminate-an-isa-bus-correctly maker.pro/forums/threads/isa-bus-termination-question.113863/
Phil: Highly informative video once again! It got me thinking that it might help the intuition if, along with the voltage waveforms (like at 18:07) comparing unterminated and terminated lines, we could also see the current waveforms in those lines. There I think termination trades some high frequency ringing current at the transitions for lower-frequency current at the fundamental frequency of the digital signal. Ie: Consider a 100MHz square wave signal: Unterminated there will be bursts of ringing current at the edges, but maybe not much at 100MHz. Whereas terminated the ringing is suppressed, but there are solid pulses of current into the terminator at 100MHz. (And that all leads to topics of track layout, return path and location of the bypass caps needed to handle driving that current, and also absorbing it at the terminator.) Anyhow, it would be reassuring to see these speculations confirmed or undermined by simulation or actual measurements!
thanks for the video
Thanks for watching!
Also routing above 45 degrees begins to introduce further reflections. I am surprised the gigabit layout didn't use the bendy wendy routing it still looks like 45/90 degrees are used?
Hello, Phil! Once you did a video about the Patch Antenna for ESP32 with Robert! Did it worked?? I didn't find any video of you testing it! I am also planning to test out similar thing in future.
It would be very interesting to see how you can terminate for multiple high speed connector footprints. If you second source and put both placements on the PCb, can you attenuate reflections introduced by the trace stubs for the unplaced alternate 🤔
As always, great video Phil! I was wondering if you know a good methodology to collaborate while creating a PCB project (from sch to layout). This is something that, i believe, would be very interesting for many people. Thank you again for your contribution to the community!
Thank you! Great idea - this is something Altium 365 is aiming to help with, however, I'll try to make a more generic ECAD tool video.
@@PhilsLab Thank you for taking me in consideration. I'll keep in touch!
Thank you very much for video! Could you explain how to choose Termination Voltage?Does It depends on?
Thanks for watching! Depends on a few factors: the specific bus/interface and its voltage(s), choosing Vt aiming to minimise avg. power consumption, etc. I'd recommend looking through the app notes in the description for detail.
Very nice video :D
Thank you!
can you set the logic family from the symbol itself? asking since setting this up for each board is not ideal. Also how you you enable simulation only on certain nets? asking since it was trying to use 12v and odd things s transmission lines? PS also how do you handle a transformer in this analysis ? as AC ?
Yes, you can add SI information when you create the schematic symbol. You have to do some set-up before performing simulations (e.g. defining power nets, using planes instead of polygon pours, etc.). Everything is document on the Altium sites.
How good was that!!
Thank you!
Does Altium have a license priced low enough for hobbyists? I couldn't find a license worthwhile for occasional use.
Hello, very interesting. What about chips with ODT? I had a design with LPDDR4X memory, and because of ODT, I didn't require termination
Thanks! LPDDR4 is a special case, as that includes termination even for 'ACC' signals. 'Normal' DDR4 will require external termination for certain signal groups.
@@PhilsLab very great. LPDDR4 seemed too easy in general. It didn't even require length matching! The only proper care needed was to keep trace impedance and avoid crosstalk / via stubs I hope to have the chance to work on something more complicated later on
Yeah, as someone making MIPI IP I was surprised why anyone would not use termination on the chip itself. After all, on-die termination can be tuned or calibrated in case of issues.
Which termination is more important, parallel or series? I guess you can't use them both at once because you would reduce signal at receiver by half. Also, apart of the case e.g. for DDR memory where those resistor are part of the design, I guess it is difficult to select value of parallel resistor - if it is too high improvement will be small, if it is too small voltage at the receiver may go down to an unacceptable levels.
*I would love to see a High Power Function Generator Amplifier* ❤❤ Maybe use the ADA4870, I had an eye on it (at least as an amateur 😅) +/- 20V, 1A, 52Mhz+, 2500 V/µs, Low noise, short-circuit and thermal protection... Sounds all good to me 🤔 Professional ones are so gosh dang expensive. For example the Siglent SPA1010, 1Mhz 10W amp, costs 400$. Why I don't get it? 😥 *Would love to see your take on it* ❤❤
Welcome back
Thank you!
How to determine the termination resistors tie to some voltages or tie to ground?
First, the particular termination voltage (VT) has no effect on the termination impedance, so you are free to choose a VT by other reasons. So the goal would be to pick VT to minimize average power dissipation. If the signal duty cycle is about 50% then VT at half of the signal amplitude would be good. But if the signal spends most of the time high, with brief low pulses, then making VT equal to the signal high voltage will save a lot of power. However, there's another thing to check, and that's the amount of "sag" due to the load of the resistor relative to the driver's current capability. As Phil shows at around 17:55, a termination resistor to ground will reduce the logic high voltage, while a resistor to VCC will raise the logic low voltage. Each of these reduces the noise margin for that level, or may even cause the signal to be unable to make it across the threshold of that level. So that has to be calculated based on the source and sink current capabilities of the drivers, and the high and low thresholds of the receivers. It's important to note that some logic families have asymmetrical output drive capabilities and/or unequal input logic level thresholds, so you have to consider all combinations. Hope that helps!
is the corrected crosstalk video still in the works?
Yes, waiting for the test boards to be manufactured!
sir what about that hades firmware we are eagerly waiting for that video
Hey Phil, surely the current cunsumption is off the charts here? But I suppose thats the price to pay for speed
Hey Marco, Yeah, it's pretty hefty in comparison to other termination techniques, but also very effective.
Would be interesting to see how bad the Overshoot/Undershoot of the ZettBrett is
Waiting to get a new scope which I'll use to check out the DDR interface! So far no problem running the interface at max. bandwidth.
very cool, cant wait for it.
@@PhilsLab I'm going to be really intrigued to see what efforts are required to minimize the effect of the scope probes (or direct connection) on that type of signal.
Hi, that was a very good lesson. You don't want to do tutorials about DC-DC converters, car inverters or passive RC and LC filters.
Thank you! I have some videos on RC filters, and DC/DC converters on my channel.
The problem with Altium SI tool is it is very buggy and hasn't been maintained or developed since 2018
I every so often think of doing something with high speed, but KiCad isn't enough (I mean manually it's possible, but some tools would be good to have) and Altium Designer is way too complex.
Unfortunately SI tools in Altium Designer are total crap compared to competition (for example it requires using plane layer type, which nobody uses nowadays, it doesn't allow selecting a set of traces to simulate as opposed to all, doesn't display locations of impedance discontinuities, etc.). Even much cheaper Cadence Orcad Pro has much more useful and functional tools for signal integrity.